Semiconductor wafers are used in the fabrication of integrated circuits (ICs) that drive modern electronic devices. The fabrication of ICs typically involve hundreds of process steps such as implantation, deposition, lithography, etching, and polishing. These process steps help in fabricating tiny (nanometer scale) structures on semiconductor wafers.
The abundance of modern electronic devices is primarily due to advances in the design and fabrication of ICs. These advances have increased processing power, memory capacity, and bandwidth in ICs. Remarkably, they have also reduced the cost of ICs. Advances in ICs are primarily made possible by node scaling and increase in wafer size. Node scaling refers to the decreasing sizes of component sizes in ICs. Increase in wafer size refers to increasing semiconductor wafer diameters. Together, node scaling and increase in wafer size allow semiconductor fabs to fabricate an increasing number of ICs on a single wafer, thereby reducing cost.
Production yield is another important factor that affects cost of ICs. Yield refers to the ratio of ICs that meet performance specifications to the total number of ICs. A lower yield results in an increased wastage of ICs, thereby increasing the cost of functional ICs. Semiconductor fabs strive to maximize yield in order to minimize cost. Maximizing yield is a challenging task because of the large number and complexity of process steps involved in IC fabrication. The determination of an IC to be non-functional at the end of fabrication does not necessarily point to the root-cause of what exactly went wrong in its exhaustive fabrication process. Knowing the root-cause is crucial to avoid propagation of fabrication errors to multiple wafers. In order to provide greater visibility into process steps, semiconductor fabs inspect wafers for abnormalities or defects after each significant process step. If a sudden increase in the number of defects is observed at a particular stage of fabrication process, steps are taken to immediately identify and eliminate the root cause of the observed defects so as to contain the undesirable yield impact due to excessive defects. First, properties of defects such as shape and size are determined. This defect information is used as an evidence to narrow down suspicious process steps that may be generating the defects. Parameters of the process steps thus identified are tuned to eliminate propagation of defects to multiple wafers.
The process of identifying root cause of defects is an exhaustive task involving multiple wafer inspection tools, resulting in an undesirable down time in semiconductor fabrication. In other words, production steps are often suspended until the root cause is identified an eliminated. This leads to a decrease in fabrication efficiency and an increase in cost. Typically, the process of identification of root cause of defects involves scanning of a semiconductor wafer with an optical wafer inspection tool. The optical wafer inspection tool provides information on position and equivalent sizes of defects. The information obtained from traditional optical wafer inspection tools is often insufficient to identify the root cause of defects. Semiconductor wafers are then scanned in electron based wafer review systems to determine the shape of defects. Electron based wafer review systems are extremely slow. In order to speed up the process of determining the shape of defects, information on position of defects obtained from optical wafer inspection tools is fed into electron based wafer review tools.
Traditional wafer inspection suffers from a number of problems: a) need for multiple systems to identify root-cause of defects, b) increased down time in fabrication, c) complex position matching requirement between multiple systems, and d) electron based review systems use high energy electron beams that could damage intricate structures on wafer.
Accordingly, there is a need for improved wafer inspection that eliminates the need for multiple systems to identify root-cause of defects, minimizes down time in fabrication, eliminates the need for complex position matching requirement between multiple systems, and eliminates use of high energy electron beams that could damage intricate structures on wafer.